About

VR Sathiyanarayana

Hi, I’m Sathiya! I’m a second-year doctoral student working with Rupak Majumdar in the Rigorous Software Engineering group at the Max Planck Institute for Software Systems in Kaiserslautern, Germany.

I’m interested in a variety of topics that fall under the umbrella of logic and computability theory. At the moment, I’m studying the structure of probabilistic programs that satisfy certain termination guarantees.

I earned my master’s at the Chennai Mathematical Institute in 2022. My master’s thesis, which you can find here, elaborates on the separation of temporal logics over ordered trees.

I maintain a (quite messy) technical diary. I (sometimes) polish up the nice bits from it and upload them here.

Here’s my resume. My publications are:

Majumdar, Rupak, & Sathiyanarayana, V. R. (2024). Positive Almost-Sure Termination – Complexity and Proof Rules. Proc. ACM Program. Lang., POPL. https://doi.org/10.1145/3632879